Recent advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Semiconductor manufacturing process advancements are driving the corresponding geometric dimensions for semiconductor devices to decreasingly smaller values. As semiconductor manufacturing processes advance, so must the corresponding simulation algorithms that are used to characterize the circuits manufactured by the advanced processes.
Semiconductor devices implemented using 130 nm process rules, for example, behave differently when those devices are implemented with sub-100 nm, e.g., 90 nm or 65 nm, process rules. In particular, negative bias and temperature instability (NBTI) is one example of a device degradation mechanism that has been identified with sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs).
NBTI causes a threshold voltage increase in P-type MOSFETs (PMOSFETs), which results in a degraded transistor current drive. Such a degradation in current drive also affects the switching speed of circuits that incorporate NBTI-affected PMOS devices. The amount of time required to switch the output of an inverter, for example, from a logic high level to a logic low level actually decreases due to the degraded current drive of the NBTI affected PMOSFET within the inverter. Conversely, the amount of time required to switch the output of the inverter from a logic low level to a logic high level increases due to the degraded current drive of the NBTI affected PMOS transistor within the inverter.
NBTI effects become prevalent when the gate of a PMOS device is negatively biased for an extended period of time, e.g., several years, at elevated temperatures. In such instances, interface traps and fixed charges are created, whereby the silicon oxide of the PMOS gate interacts with the crystal lattice of the silicon substrate to trap holes, i.e., positive charge, within the channel inversion layer. The fixed charges and interface traps are of the same polarity, i.e., positive, and combine to increase the threshold voltage, VT, of the PMOS device.
Due to the NBTI phenomenon, therefore, designers must consider the bias conditions of each PMOS transistor throughout the PMOS transistor's lifetime. Typically, consideration of the bias conditions must allow for at least 10 years of operation in a conductive state at high temperature. In a particular simulation scenario, therefore, two PMOS transistor models may exist: a first PMOS model having normal threshold voltage, i.e., a PMOS model that is not affected by the NBTI phenomenon; and a second PMOS model exhibiting increased threshold voltage due to the NBTI phenomenon.
Prior art simulation methods have incorporated a manual process, whereby the circuit designer first identifies those PMOS transistors in the simulation netlist that are in a conductive state. Next, the circuit designer manually replaces all conductive PMOS transistor models with PMOS transistor models exhibiting increased threshold voltage due to the NBTI phenomenon. Finally, the circuit designer executes the simulation on the manually modified simulation netlist.
Such a manual simulation process may be plausible for relatively small netlists. However, the manual simulation process quickly becomes unmanageable and cumbersome for larger netlists. What is needed then, is an automated technique to simulate the affect of the NBTI phenomenon on deep, sub-100 nm circuits using existing simulation technologies.